HD6417618 datasheet(436/646 Pages) RENESAS

436 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 404 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

EIC6

EIC5

EIC4

EIC3

EIC2

EIC1

EIC0

R/W

External Interrupt Source

These bits specify the source for interrupts generated by

the EIR bit. These bits can be written to from both an

external device and the on-chip CPU. By using these

bits, fast execution of interrupt exception handling is

possible. These bits are completely under software

control, and their values have no effect on the operation

of this LSI.

EIR

R/W

External Interrupt Request

While this bit is 1, the

HIFINT pin is asserted to issue an

interrupt request to an external device from this LSI.

15.4.7

HIF Address Register (HIFADR)

HIFADR is a 32-bit register which indicates the address in HIFRAM to be accessed by an external

device. When using the LOCK bit setting in HIFMCR to specify consecutive access of HIFRAM,

auto-increment (+4) or auto-decrement (-4) of the address, according to the AI/AD bit setting in

HIFMCR, is performed automatically, and HIFADR is updated. HIFADR can be only read by the

on-chip CPU. Access to HIFADR by an external device should be performed with HIFADR

specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 10

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

9 to 2

A9 to A2

All 0

R/W*

HIFRAM Address Specification

These bits specify the address of HIFRAM to be

accessed by an external device, with 32-bit boundary.

1, 0

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

Note:

This bit can be only written to by an external device when the HIFRS pin is low. It

cannot be written to by the on-chip CPU.

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