HD6417618 datasheet(433/646 Pages) RENESAS

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Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 401 of 610

REJ09B0131-0600

15.4.4

HIF Memory Control Register (HIFMCR)

HIFMCR is a 32-bit register used to control HIFRAM. HIFMCR can be only read by the on-chip

CPU. Access to HIFMCR by an external device should be performed with HIFMCR specified by

bits REG5 to REG0 in HIFIDX and the HIFRS pin low.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 8 —

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

LOCK

R/W*

Lock

This bit is used to lock the access direction (read or write)

for consecutive access of HIFRAM by an external device

via HIFDATA. When this bit is set to 1, the values of the

RD and WT bits set at the same time are held until this

bit is next cleared to 0. When the RD bit and this bit are

simultaneously set to 1, consecutive read mode is

entered. When the WT bit and this bit are simultaneously

set to 1, consecutive write mode is entered. Both the RD

and WT bits should not be set to 1 simultaneously.

—

Reserved

This bit is always read as 0. The write value should

always be 0.

R/W*

Write

When this bit is set to 1, the HIFDATA value is written to

the HIFRAM position corresponding to HIFADR.

If this bit and the LOCK bit are set to 1 simultaneously,

HIFRAM consecutive write mode is entered, and high-

speed data transfer becomes possible. This mode is

maintained until this bit is next cleared to 0, or until the

LOCK bit is cleared to 0.

If the LOCK bit is not simultaneously set to 1 with this bit,

writing to HIFRAM is performed only once. Thereafter,

the value of this bit is automatically cleared to 0.

—

Reserved

This bit is always read as 0. The write value should

always be 0.

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