HD6417618 datasheet(430/646 Pages) RENESAS

430 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 398 of 610

REJ09B0131-0600

15.4.2

HIF General Status Register (HIFGSR)

HIFGSR is a 32-bit register, which can be freely used for handshaking between an external device

connected to the HIF and the software of this LSI. HIFGSR can be read from and written to by the

on-chip CPU. Reading from HIFGSR by an external device should be performed with the HIFRS

pin high, or HIFGSR specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low. Writing

to HIFGSR by an external device should be performed with HIFGSR specified by bits REG5 to

REG0 in HIFIDX and the HIFRS pin low.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 16

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

15 to 0

STATUS15 to

STATUS0

All 0

R/W

General Status

This register can be read from and written to by an

external device connected to the HIF, and by the

on-chip CPU. These bits are initialized only at a

power-on reset.

15.4.3

HIF Status/Control Register (HIFSCR)

HIFSCR is a 32-bit register used to control the HIFRAM access mode and endian setting.

HIFSCR can be read from and written to by the on-chip CPU. Access to HIFSCR by an external

device should be performed with HIFSCR specified by bits REG5 to REG0 in HIFIDX and the

HIFRS pin low.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 12

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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