HD6417618 datasheet(434/646 Pages) RENESAS

434 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 402 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

R/W*

Read

When this bit is set to 1, the HIFRAM data corresponding

to HIFADR is fetched to HIFDATA.

If this bit and the LOCK bit are set to 1 simultaneously,

HIFRAM consecutive read mode is entered, and high-

speed data transfer becomes possible. This mode is

maintained until this bit is next cleared to 0, or until the

LOCK bit is cleared to 0.

If the LOCK bit is not simultaneously set to 1 with this bit,

reading of HIFRAM is performed only once. Thereafter,

the value of this bit is automatically cleared to 0.

2, 1

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

AI/AD

R/W*

Address Auto-Increment/Decrement

This bit is valid only when the LOCK bit is 1. The value of

HIFADR is automatically incremented by 4 or

decremented by 4 according to the setting of this bit each

time reading or writing of HIFRAM is performed.

0: Auto-increment mode (+4)

1: Auto-decrement mode (

−4)

Note:

This bit can be only written to by an external device when the HIFRS pin is low. It

cannot be written to by the on-chip CPU. Changing the HIFRAM banks accessible from

an external device by setting the BMD and BSEL bits in HIFSCR does not affect the

setting of this bit.

HD6417618 Datasheet(PDF) 434 Page - Renesas Technology Corp

HD6417618 Datasheet(HTML) 434 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL