HD6417618 datasheet(439/646 Pages) RENESAS

439 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 407 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

DTRG

R/W*

1 *2 HIFDREQ Trigger

When 1 is written to this bit, the HIFDREQ pin is

asserted according to the setting of the DMD and

DPOL bits in HIFSCR. This bit is automatically

cleared to 0 in synchronization with negate of the

HIFDREQ pin.

Though this bit can be set to 1 by the on-chip CPU, it

cannot be cleared to 0.

To avoid conflict between clearing of this bit by

negate of the HIFDREQ pin and setting of this bit by

the on-chip CPU, make sure this bit is cleared to 0

before setting this bit to 1 by the on-chip CPU.

Notes: 1. This bit cannot be accessed by an external device. It can be accessed only by the on-

chip CPU.

2. Writing 0 to this bit by the on-chip CPU is ignored.

15.4.11

HIF Bank Interrupt Control Register (HIFBICR)

HIFBICR is a 32-bit register that controls HIF bank interrupts. HIFBICR cannot be accessed by an

external device.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 2

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

BIE

R/W*

Bank Interrupt Enable

Enables or disables a bank interrupt request (HIFBI)

issued to the on-chip CPU.

0: HIFBI disabled

1: HIFBI enabled

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