HD6417618 datasheet(441/646 Pages) RENESAS

441 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 409 of 610

REJ09B0131-0600

15.5

Memory Map

Table 15.3 shows the memory map of HIFRAM.

Table 15.3

Memory Map

Classification

Start Address

End Address

Memory Size

Map from external device*

H'0000

H'03FF

1 kbyte

Map from on-chip CPU*

1 *2

H'F84E0000

H'F84E03FF

1 kbyte

Notes: 1. Map for a single HIFRAM bank. Which bank is to be accessed by an external device or

the on-chip CPU depends on the BMD and BSEL bits in HIFSCR. The mapping

addresses are common between the banks.

2. Note that in HIF boot mode, bank 0 is selected, and the first 1 kbyte in each of the

following address ranges are also mapped: H'00000000 to H'01FFFFFF (first-half 32

Mbytes of area 0 in the P0 area), H'20000000 to H'21FFFFFF (first-half 32 Mbytes of

area 0 in the P0 area), H'40000000 to H'41FFFFFF (first-half 32 Mbytes of area 0 in the

P0 area), H'60000000 to H'61FFFFFF (first-half 32 Mbytes of area 0 in the P0 area),

H'80000000 to H'81FFFFFF (first-half 32 Mbytes of area 0 in the P1 area), H'A0000000

to H'A1FFFFFF (first-half 32 Mbytes of area 0 in the P2 area), and H'C0000000 to

H'C1FFFFFF (first-half 32 Mbytes of area 0 in the P3 area).

If an external device modifies HIFRAM when HIFRAM is accessed from the P0, P1, or

P3 area with the cache enabled, coherency may not be ensured. When the cache is

enabled, accessing HIFRAM from the P2 area is recommended.

In HIF boot mode, among the first-half 32 Mbytes of each area 0, access to the areas to

which HIFRAM is not mapped is inhibited.

Even in HIF boot mode, the second-half 32 Mbytes of area 0, area 3, area 4, area 5B,

area 5, area 6B, and area 6 are mapped to the external memory as normally.

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