HD6417618 datasheet(228/646 Pages) RENESAS

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Section 8 Clock Pulse Generator (CPG)

Rev. 6.00 Jun. 12, 2007 Page 196 of 610

REJ09B0131-0600

PHY-LSI Clock Frequency Control Register: The PHY-LSI clock frequency control register

sets the frequency division ratio of the PHY-LSI clock.

8.2

Input/Output Pins

Table 8.1 shows the CPG pin configuration.

Table 8.1

Pin Configuration

Pin Name

Abbr.

I/O

Description

Mode control pins*

MD0

Input

Set the clock operating mode.

MD1

Input

Set the clock operating mode.

MD2

Input

Set the clock operating mode.

Clock input pins

XTAL

Output

Connects a crystal resonator.

EXTAL

Input

Connects a crystal resonator or an external clock.

Clock output pin

CKIO

Output

Outputs an external clock.

PHY-LSI clock pin

CK_PHY Output

Outputs a clock for an external PHY-LSI.

Note:

The values of these mode control pins are sampled only at a power-on reset or in a

software standby with the MDCHG bit in STBCR to 1. This can prevent the erroneous

operation of this LSI.

8.3

Clock Operating Modes

Table 8.2 shows the relationship between the mode control pins (MD2 to MD0) combinations and

the clock operating modes. Table 8.3 shows the usable frequency ranges in the clock operating

modes and the frequency range of the input clock.

Table 8.2

Mode Control Pins and Clock Operating Modes

Pin Values

Clock I/O

Clock

Operating

Mode

MD2 MD1 MD0

Source

Output

PLL2

PLL1

CKIO Frequency

EXTAL

CKIO

ON (

×4)

ON (

×1, ×2) (EXTAL) × 4

Crystal resonator

CKIO

ON (

×4)

ON (

×1, ×2) (Crystal resonator) × 4

EXTAL

CKIO

ON (

×2)

ON (

×1, ×2) (EXTAL) × 2

Crystal resonator

CKIO

ON (

×2)

ON (

×1, ×2) (Crystal resonator) × 2

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