HD6417618 datasheet(225/646 Pages) RENESAS

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Section 8 Clock Pulse Generator (CPG)

CPGS301C_000020030900

Rev. 6.00 Jun. 12, 2007 Page 193 of 610

REJ09B0131-0600

Section 8 Clock Pulse Generator (CPG)

This LSI has a clock pulse generator (CPG) that generates an internal clock (I

φ), a peripheral clock

φ), a bus clock (Bφ) and a clock (Mφ) for an IEEE802.3-PHY (physical layer device),

hereinafter called PHY-LSI. The CPG consists of an oscillator, PLL circuits, and divider circuits.

8.1

Features

• Four clock modes

Selection of four clock modes depending on the frequency of a clock source and whether a

crystal resonator or external clock input is in use.

• Four clocks generated independently

An internal clock (I

φ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip

peripheral modules; a bus clock (B

φ = CKIO) for the external bus interface; and a clock (Mφ)

for the PHY-LSI.

• Frequency change function

Frequencies of the internal clock, peripheral clock, and clock for the PHY-LSI can be changed

independently using the PLL circuit and divider circuit within the CPG. Frequencies are

changed by software using the frequency control register (FRQCR) and PHY-LSI clock

frequency control register (MCLKCR) settings.

• Power-down mode control

The clock can be stopped in sleep mode and software standby mode and specific modules can

be stopped using the module standby function.

HD6417618 Datasheet(PDF) 225 Page - Renesas Technology Corp