HD6417618 datasheet(222/646 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 190 of 610

REJ09B0131-0600

7.5.8

Wait between Access Cycles

Data output in the previous cycle may conflict with that in the next cycle because the buffer-off

timing of devices with slow access speed cannot be operated to satisfy the higher operating

frequency of LSIs. As a result of these conflict, the reliability of the device is low and

malfunctions may occur. This LSI has a function that avoids data conflicts by inserting wait cycles

between consecutive access cycles.

The number of wait cycles between access cycles can be set by bits IWW1 and IWW0, bits

IWRWD1 and IWRWD0, bits IWRWS1 and IWRWS0, bits IWRRD1 and IWRRD0, and bits

IWRRS1 and IWRRS0 in CSnBCR. The conditions for setting the wait cycles between access

cycles (idle cycles) are shown below.

1. Consecutive accesses are write-read or write-write

2. Consecutive accesses are read-write for different areas

3. Consecutive accesses are read-write for the same area

4. Consecutive accesses are read-read for different areas

5. Consecutive accesses are read-read for the same area

7.5.9

Others

Reset: The bus state controller (BSC) can be initialized completely only by a power-on reset. At

power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle

state. All control registers are initialized. In standby mode and sleep mode, control registers of the

BSC are not initialized.

Some flash memories may stipulate a minimum time from reset release to the first access. To

ensure this minimum time, the BSC supports a 7-bit counter (RWTCNT). At a power-on reset, the

RWTCNT contents are cleared to 0. After a power-on reset, RWTCNT is counted up in

synchronization with the CKIO signal and an external access will not be generated until RWTCNT

is counted up to H'007F.

Access from the Site of the LSI Internal Bus Master: There are three types of LSI internal

buses: a cache bus, internal bus, and peripheral bus. The CPU and cache memory are connected to

the cache bus. Internal bus masters other than the CPU and BSC are connected to the internal bus.

Low-speed peripheral modules are connected to the peripheral bus. Internal memory other than the

cache memory and debugging modules such as the UBC are connected to both the cache bus and

internal bus. Access from the cache bus to the internal bus is enabled but access from the internal

bus to the cache bus is disabled. This gives rise to the following problems.

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