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HD6417618 Datasheet(PDF) 219 Page - Renesas Technology Corp

Part # HD6417618
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618 Datasheet(HTML) 219 Page - Renesas Technology Corp

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Section 7 Bus State Controller (BSC)
Rev. 6.00 Jun. 12, 2007 Page 187 of 610
REJ09B0131-0600
PCMCIA interface area is 32 Mbytes (An I/O port pin is used as the
REG)
Area 5 : H'14000000
Attribute memory/common memory
I/O space
Attribute memory/common memory
I/O space
Area 5 : H'16000000
Area 6 : H'18000000
Area 6 : H'1A000000
PCMCIA interface area is 16 Mbytes (A24 is used as the
REG)
Area 5 : H'14000000
Attribute memory
I/O space
Area 5 : H'15000000
Area 5 : H'16000000
H'17000000
Area 6 : H'18000000
Area 6 : H'19000000
Area 6 : H'1A000000
H'1B000000
Common memory
Attribute memory
I/O space
Common memory
Figure 7.33 Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B'10,
CS6BWCR.SA[1:0] = B'10)
Basic Timing for I/O Card Interface: Figures 7.34 and 7.35 show the basic timings for the
PCMCIA I/O card interface.
The I/O card and IC memory card interfaces are specified by an address to be accessed. When
area 5 of the physical space is specified as the PCMCIA and both bits SA1 and SA0 in CS5BWCR
are set to 1, the I/O card interface can automatically be specified by accessing the physical
addresses from H'16000000 to H'17FFFFFF and from H'14000000 to H'15FFFFFF. When area 6
of the physical space is specified as the PCMCIA and both bits SA1 and SA0 in CS6BWCR are
set to 1, the I/O card interface can automatically be specified by accessing the physical addresses
from H'1A000000 to H'1BFFFFFF and from H'18000000 to H'19FFFFFF.
Note that areas to be accessed as the PCMCIA I/O card must be non-cached (space P2).
If the PCMCIA card is accessed as an I/O card in little endian mode, dynamic bus sizing for the
I/O bus can be achieved using the
IOIS16 signal. If the IOIS16 signal is driven high in a word-size
I/O bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized as 8
bits and data is accessed twice in units of eight bits in the I/O bus cycle to be executed.



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