HD6417618 datasheet(224/646 Pages) RENESAS

Part #	HD6417618

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 192 of 610

REJ09B0131-0600

In read cycles, the CPU is placed in the wait cycle until read operation has been completed. To

continue the process after the data write to the device has been completed, perform a dummy read

to the same address to check for completion of the write before the next process to be executed.

The write buffer of the BSC functions in the same way for an access by a bus master other than the

CPU such as the DMAC or E-DMAC. Accordingly, to perform dual address DMA transfers, the

next read cycle is initiated before the previous write cycle is completed. Note, however, that if

both the DMA source and destination addresses exist in external memory space, the next write

cycle will not be initiated until the previous write cycle is completed.

On-Chip Peripheral Module Access: To access an on-chip module register, two or more

peripheral module clock (P

φ) cycles are required. Care must be taken in system design.

HD6417618 Datasheet(PDF) 224 Page - Renesas Technology Corp