HD6417618 datasheet(232/646 Pages) RENESAS

Part #	HD6417618

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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232 / 646 page

Section 8 Clock Pulse Generator (CPG)

Rev. 6.00 Jun. 12, 2007 Page 200 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

PFC2

PFC1

PFC0

R/W

Peripheral Clock Frequency Division Ratio

Specify the division ratio of the peripheral clock

frequency with respect to the output frequency of PLL

circuit 1.

000:

×1

001:

×1/2

011:

×1/4

Other values: Setting prohibited

8.4.2

PHY-LSI Clock Frequency Control Register (MCLKCR)

MCLKCR is an 8-bit readable/writable register. This register must be written to in words. The

upper byte of the word data must be H'5A and the lower byte is the write data.

Bit

Bit Name

Initial

Value

R/W

Description

FLSCS1

FLSCS0

R/W

Source Clock Select

Select the source clock.

00: PLL1 output clock

01: PLL1 output clock

10: Setting prohibited

11: Setting prohibited

5 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

FLDIVS2

FLDIVS1

FLDIVS0

R/W

Divider Select

Set the division ratio of PLL1 output.

000:

×1

001:

×1/2

011:

×1/4

Other values: Setting prohibited

HD6417618 Datasheet(PDF) 232 Page - Renesas Technology Corp

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