HD6417618 datasheet(234/646 Pages) RENESAS

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Section 8 Clock Pulse Generator (CPG)

Rev. 6.00 Jun. 12, 2007 Page 202 of 610

REJ09B0131-0600

8.5

Changing Frequency

The internal clock frequency can be changed by changing the multiplication ratio of PLL circuit 1.

The peripheral clock frequency can be changed either by changing the multiplication ratio of PLL

circuit 1 or by changing the division ratio of divider 1. All of these are controlled by software

through the frequency control register. The methods are described below.

8.5.1

Changing Multiplication Ratio

The PLL lock time must be preserved when the multiplication ratio of PLL circuit 1 is changed.

The on-chip WDT counts for preserving the PLL lock time.

1. In the initial state, the multiplication ratio of PLL circuit 1 is 1.

2. Set a value that satisfies the given PLL lock time in the WDT and stop the WDT. The

following must be set.

 TME bit in WTCSR = 0: WDT stops

 Bits CKS2 to CKS0 in WTCSR: Division ratio of WDT count clock

 WTCNT: Initial counter value

3. Set the desired value in bits STC2 to STC0 while the MDCHG bit in STBCR is 0. The division

ratio can also be set in bits PFC2 to PFC0.

4. This LSI pauses internally and the WDT starts incrementing. The internal and peripheral

clocks both stop and only the WDT is supplied with the clock. The clock will continue to be

output on the CKIO pin.

5. Supply of the specified clock starts at a WDT count overflow, and this LSI starts operating

again. The WDT stops after it overflows.

Notes: 1. When the MDCHG bit in STBCR is set to 1, changing the FRQCR value has no effect

on the operation immediately. For details, see section 8.5.3, Changing Clock Operating

Mode.

2. The multiplication ratio should be changed after completion of the operation, if the on-

chip peripheral module is operating. The internal and peripheral clocks are stopped

during the multiplication ratio is changed. The communication error may occur by the

peripheral module communicating to the external IC, and the time error may occur by

the timer unit (except the WDT). The edge detection of external interrupts (NMI and

IRQ7 to IRQ0) cannot be performed.

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