HD6417618 datasheet(231/646 Pages) RENESAS

231 / 646 page

Section 8 Clock Pulse Generator (CPG)

Rev. 6.00 Jun. 12, 2007 Page 199 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

15 to 13



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

CKOEN

R/W

Clock Output Enable

Specifies whether a clock continues to be output from

the CKIO pin or the output level of the CKIO signal is

fixed when leaving software standby mode. The CKIO

output is fixed low when this bit is set to 0. Therefore,

the malfunction of external circuits because of an

unstable CKIO clock when leaving software standby

mode can be prevented.

0: Output level of the CKIO signal is fixed low in

software standby mode.

1: Clock input to the EXTAL pin is output to the CKIO

pin during software standby mode in clock mode 1

or 5. However, the output level of the CKIO pin is

fixed low for two cycles of P

φ when changing from

the normal mode to the standby mode. This

prevents hazard which occurs when the source of

the CKIO signal is changed from the PLL2 output

to the EXTAL signal.



Reserved

This bit is always read as 0. The write value should

always be 0.

STC2

STC1

STC0

R/W

PLL Circuit 1 Frequency Multiplication Ratio

000:

×1

001:

×2

Other values: Setting prohibited

7 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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