HD6417618 datasheet(405/646 Pages) RENESAS

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Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 373 of 610

REJ09B0131-0600

In serial reception, the SCIF operates as described below.

1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal

synchronization and starts reception.

2. The received data is stored in SCRSR in LSB-to-MSB order.

3. The parity bit and stop bit are received.

After receiving these bits, the SCIF carries out the following checks.

A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only

the first is checked.

B. The SCIF checks whether receive data can be transferred from the receive shift register

(SCRSR) to SCFRDR.

C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error

has not occurred.

D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not

set.

If all the above checks are passed, the receive data is stored in SCFRDR.

Note:

When a parity error or a framing error occurs, reception is not suspended.

4. If the RIE bit in SCSCR is set to 1 when the RDF or DR flag changes to 1, a receive-FIFO-

data-full interrupt (RXI) request is generated. If the RIE bit or the REIE bit in SCSCR is set to

1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the

RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a

break reception interrupt (BRI) request is generated.

HD6417618 Datasheet(PDF) 405 Page - Renesas Technology Corp