HD6417618 datasheet(408/646 Pages) RENESAS

408 / 646 page

Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 376 of 610

REJ09B0131-0600

Communication Format: The data length is fixed at eight bits. No parity bit can be added.

Clock: An internal clock generated by the on-chip baud rate generator or an external clock input

from the SCK pin can be selected as the SCIF transmit/receive clock.

When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight

clock pulses are output per transmitted or received character. When the SCIF is not transmitting or

receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs

while the RE bit of SCSCR is 1 and the number of data in receive FIFO is less than the receive

FIFO data trigger number. In this case, 8

× (16 + 1) = 136 pulses of synchronous clock are output.

To perform reception of n characters of data, select an external clock as the clock source. If an

internal clock should be used, set RE = 1 and TE = 1 and receive n characters of data

simultaneously with the transmission of n characters of dummy data.

Transmitting and Receiving Data SCIF Initialization (Synchronous Mode): Before

transmitting, receiving, or changing the mode or communication format, the software must clear

the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF. Clearing

TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not

initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which retain

their previous contents.

Figure 14.12 shows a sample flowchart for initializing the SCIF. The procedure for initializing the

SCIF is:

HD6417618 Datasheet(PDF) 408 Page - Renesas Technology Corp