34708 datasheet(109/159 Pages) FREESCALE

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Analog Integrated Circuit Device Data



109

Freescale Semiconductor

MC34708

Functional Block Description

7.9.1.2

SPI Timing Requirements

The following diagram and table summarize the SPI timing requirements. The SPI input and output levels are set via the SPIVCC

pin, by connecting it to the desired supply. This would typically be tied to SW5 and programmed for 1.80 V. The strength of the

MISO driver is programmable through the SPIDRV [1:0] bits. See Thermal Protection Thresholds for detailed SPI electrical

characteristics.

Figure 35. SPI Interface Timing Diagram

Table 99. SPI Interface Timing Specifications(72)

Parameter

Description

T min (ns)

tSELSU

Time CS has to be high before the first rising edge of CLK

tSELHLD

Time CS has to remain high after the last falling edge of CLK

tSELLOW

Time CS has to remain low between two transfers

tCLKPER

Clock period of CLK

tCLKHIGH

Part of the clock period where CLK has to remain high

tCLKLOW

Part of the clock period where CLK has to remain low

tWRTSU

Time MOSI has to be stable before the next rising edge of CLK

4.0

tWRTHLD

Time MOSI has to remain stable after the rising edge of CLK

4.0

tRDSU

Time MISO will be stable before the next rising edge of CLK

4.0

tRDHLD

Time MISO will remain stable after the falling edge of CLK

4.0

tRDEN

Time MISO needs to become active after the rising edge of CS

4.0

tRDDIS

Time MISO needs to become inactive after the falling edge of CS

4.0

Notes

72.

This table reflects a maximum SPI clock frequency of 26 MHz.

CLK

MOSI

MISO

tCLKPER

tCLKLOW

tDKHIGH

tSELSU

tSELHLD

tSELLOW

tRDDIS

tRDHLD

tRDSU

tRDEN

tWRTSU

tWRTHLD

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