34708 datasheet(62/159 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

MC34708

Functional Block Description

7.5.4.8

Dynamic Voltage Scaling

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the

processor. SW1A/B and SW2 allow for two different set points with controlled transitions to avoid sudden output voltage changes,

which could cause logic disruptions on their loads.

Preset operating points for SW1A/B and SW2 can be set up for:

• Normal operation: output value selected by SPI bits SWx[5:0]. Voltage transitions initiated by SPI writes to SWx[5:0] are

governed by the DVS stepping rate shown in the following tables.

• Standby (Deep Sleep): can be higher or lower than normal operation, but is typically selected to be the lowest state retention

voltage of a given process. Set by SPI bits SWxSTBY[5:0] and controlled by a Standby event. Voltage transitions initiated by

Standby are governed by the SWxDVSSPEED[1:0] SPI bits shown in Table 49.

The following table summarizes the set point control and DVS time stepping applied to SW1A/B and SW2.

The Regulator have a strong sourcing and sinking capability in the PWM mode. Therefore, the rising/falling slope is determined

by the regulator in PWM mode, however, if the regulators are programmed in PFM, PWMPS, or APS mode during a DVS

transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced,

controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode

operation.

Voltage transitions programmed through SPI(SWx[4:0]) on SW3 and SW5 will step in increments of 25 mV per 4.0

s, SW4A/B

will step in increments of 25 mV per 8.0

s when SW4xHI[1:0]=00, and SW4A/B will step in increments of 25 mV per 16 s when

SW4xHI[1:0]=00. Additionally, SW3, SW4/B, and SW5 include standby mode set point programmability.

The following diagram shows the general behavior for the switching regulators when initiated with SPI programming or standby

control.

SW1 and SW2 also contain Power Good (outputs from the MC34708 to the application processor). The power good signal is an

active high signal. When SWxPWRGDB is high, it means that the regulators output has reached its programmed voltage. The

SWxPWRGDB voltage outputs will be low during the DVS period and if the current limit is reached on the switching regulator.

The SWxPWRGD will be low from a low to high or a high to low transition of the regulator output voltage. During the DVS period,

the over-current condition on the switching regulator should be masked. If the current limit is reached outside of a DVS period,

the SWxPWRGD pin will stay low until the current limit condition is removed.

Table 49. DVS Control Logic Table for SW1A/B and SW2

STANDBY

Set Point Selected by

SWx[4:0]

SWxSTBY[4:0]

Table 50. DVS Speed Selection

SWxDVSSPEED[1:0]

Function

12.5 mV step each 2.0

s

01 (default)

12.5 mV step each 4.0

s

12.5 mV step each 8.0

s

12.5 mV step each 16.0

s

34708 Datasheet(PDF) 62 Page - Freescale Semiconductor, Inc

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