34708 datasheet(37/159 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

MC34708

Functional Block Description

The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks.

When expired, the Wait mode is exited for User Off mode or Memory Hold mode depending on warm starts being enabled or not

via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low.

7.5.2.7

Memory Hold and User Off (Low Power Off states)

As noted in the User Off Wait description, the system is directed into low power Off states based on a SPI command in response

to an intentional turn off by the end user. The only exit then will be a turn on event. To an end user, the Memory Hold and User

Off states look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external

memory in self-refresh mode (Memory Hold and User Off mode) as well as powering portions of the processor core for state

retention (User Off only). The Switching regulator mode control bits allow selective powering of the buck regulators for optimizing

the supply behavior in the low power Off modes. Linear regulators and most functional blocks are disabled (the RTC module, SPI

bits resetting with RTCPORB, and Turn On event detection are maintained).

By way of example, the following descriptions assume the typical use case where SW1 supplies the processor core(s), SW2 is

applied to the processor’s VCC domain, SW3 supplies the processors internal memory/peripherals, and SW4 supplies the

external memory, and SW5 supplies the I/O rail. The buck regulators are intended for direct connection to the aforementioned

loads.

7.5.2.8

Memory Hold

RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). To

ensure that SW1, SW2, SW3, and SW5 shut off in Memory Hold, appropriate mode settings should be used such as

SW1MHMODE, = SW2MHMODE, = SW3MHMODE, = SW5MHMODE set to = 0 (refer to the mode control description later in

this section). Since SW4 should be powered in PFM mode, SW4MHMODE could be set to 1.

Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and the MEMHLDI interrupt bit is

set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since

software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot.

No specific timer is running in this mode.

Buck regulators that are configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when

coming out of MEMHOLD and entering a Warm Boot. The switching regulators will be reconfigured for their default settings as

selected by the PUMSx pins in the normal time slot that would affect them.

7.5.2.9

User Off

RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected

to the processor’s CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM

is set.

The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1 and/or SW2 and or SW3 supply domains can

be configured for SWxUOMODE=1 to keep them powered through the User Off event. If one of the switching regulators can be

shut down in User Off, its mode bits would typically be set to 0.

Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the

processor’s state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be used

for very low frequency / low power idling of the core(s), minimizing battery drain, while allowing a rapid recovery from where the

system left off before the USEROFF command.

Upon a Turn On event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off

will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with

external memory. No specific timer is running in this mode.

7.5.2.10 Warm Start

Entered upon a Turn On event from User Off. The first 8.0 ms is used for initialization, which includes bias generation, PUMSx

latching, and qualification of the input supply level BP. The switching and linear regulators are then powered up sequentially to

limit the inrush current; see Startup Requirements for sequencing and default level details. If SW1, SW2, SW3, SW4, and/or

SW5, were configured to stay on in User Off mode by their SWxUOMODE settings, they will not be turned off when coming out

34708 Datasheet(PDF) 37 Page - Freescale Semiconductor, Inc

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