34708 datasheet(110/159 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

110

MC34708

Functional Block Description

7.9.2

I2C Interface

7.9.2.1

I2C Configuration

When configured for I2C mode, the interface may be used to access the complete register map previously described for SPI

access. Since SPI configuration is more typical, references within this document will generally refer to the common register set

as a “SPI map” and bits as “SPI bits”; however, it should be understood that access reverts to I2C mode when configured as such.

The SPI pins CLK and MISO are reused for the SCL and SDA lines respectively. Selection of I2C mode for the interface is

configured by hard-wiring the CS pin to VCOREDIG on the application board. The state of CS is latched in during the initialization

phase of a Cold Start sequence, so the I2CS bit is defined for bus configuration before the interface is activated. The pull-down

on CS will be deactivated if the high state is detected (indicating I2C mode).

In I2C mode, the MISO pin is connected to the bus as an open drain driver, and the logic level is set by an external pull-up. The

part can function only as an I2C slave device, not as a host.

7.9.2.2

I2C Device ID

I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for

bus conflict avoidance, pin programmable selection is provided to allow configuration for the address LSB(s). This product

supports 7-bit addressing only; support is not provided for 10-bit or general Call addressing.

Because the MOSI pin is not utilized for I2C communication, it is reassigned for pin programmable address selection by

hardwiring to VCOREDIG or GND at the board level when configured for I2C mode. MOSI will act as Bit 0 of the address. The

I2C address assigned to FSL PM ICs (shared amongst our portfolio) is given as follows:

00010-A1-A0, the A1 and A0 bits are allowed to be configured for either 1 or 0. The A1 address bit is internally hardwired as a

“0”, leaving the LSB A0 for board level configuration. The designated address then is defined as: 000100-A0.

7.9.2.3

I2C Operation

The I2C mode of the interface is implemented generally following the Fast Mode definition which supports up to 400 kbits/s

operation. (Exceptions to the standard are noted to be 7-bit only addressing, and no support for general Call addressing) Timing

diagrams, electrical specifications, and further details on this bus standard, is available on the internet, by typing



“I2C specification” in the web search string field.

Standard I2C protocol utilizes bytes of 8 bits, with an acknowledge bit (ACK) required between each byte. However, the number

of bytes per transfer is unrestricted. The register map is organized in 24 bit registers which corresponds to the 24 bit words

supported by the SPI protocol of this product. To ensure that I2C operation mimics SPI transactions in behavior of a complete 24

bit word being written in one transaction, software is expected to perform write transactions to the device in 3-byte sequences,

beginning with the MSB. Internally, data latching will be gated by the acknowledge at the completion of writing the third

consecutive byte.

Failure to complete a 3-byte write sequence will abort the I2C transaction and the register will retain its previous value. This could

be due to a premature STOP command from the master, for example.

I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and

3-bytes will be sent out unless a STOP command or NACK is received prior to completion.

The following examples show how to write and read data to the IC. The host initiates and terminates all communication. The host

sends a master command packet after driving the start condition. The device will respond to the host if the master command

packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK

to transmissions from the host. If at any time a NAK is received, the host should terminate the current transaction and retry the

transaction.

34708 Datasheet(PDF) 110 Page - Freescale Semiconductor, Inc

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