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HD6417618 Datasheet(PDF) 292 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 292 Page - Renesas Technology Corp |
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292 / 646 page  Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC) Rev. 6.00 Jun. 12, 2007 Page 260 of 610 REJ09B0131-0600 12.2 Register Descriptions The E-DMAC has the following registers. For addresses and access sizes of these registers, see section 20, List of Registers. • E-DMAC mode register (EDMR) • E-DMAC transmit request register (EDTRR) • E-DMAC receive request register (EDRRR) • Transmit descriptor list address register (TDLAR) • Receive descriptor list address register (RDLAR) • EtherC/E-DMAC status register (EESR) • EtherC/E-DMAC status interrupt permission register (EESIPR) • Transmit/receive status copy enable register (TRSCER) • Receive missed-frame counter register (RMFCR) • Transmit FIFO threshold register (TFTR) • FIFO depth register (FDR) • Receiving method control register (RMCR) • E-DMAC operation control register (EDOCR) • Receive buffer write address register (RBWAR) • Receive descriptor fetch address register (RDFAR) • Transmit buffer read address register (TBRAR) • Transmit descriptor fetch address register (TDFAR) • Flow control FIFO threshold register (FCFTR) • Transmit interrupt register (TRIMD) |
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