HD6417618 datasheet(291/646 Pages) RENESAS

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

EDMAS20C_000020030900

Rev. 6.00 Jun. 12, 2007 Page 259 of 610

REJ09B0131-0600

Section 12 Ethernet Controller Direct Memory Access

Controller (E-DMAC)

This LSI includes a direct memory access controller (E-DMAC) directly connected to the Ethernet

controller (EtherC). A large proportion of buffer management is controlled by the E-DMAC itself

using descriptors. This lightens the load on the CPU and enables efficient data transfer control to

be achieved.

Figure 12.1 shows the configuration of the E-DMAC, and the descriptors and transmit/receive

buffers in memory.

12.1

Features

The E-DMAC has the following features:

• The load on the CPU is reduced by means of a descriptor management system

• Transmit/receive frame status information is indicated in descriptors

• Achieves efficient system bus utilization through the use of block transfer (16-byte units)

• Supports single-frame/multi-buffer operation

Transmit

FIFO

Receive

FIFO

Transmit

descriptor

Transmit

buffer

Receive

buffer

Receive

descriptor

External bus

interface

Internal bus

Internal

bus

interface

This LSI

External memory

EtherC

E-DMAC

Descriptor

information

Transmit

DMAC

Receive

DMAC

Descriptor

information

Figure 12.1 Configuration of E-DMAC, and Descriptors and Buffers

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