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HD6417618 Datasheet(PDF) 270 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 270 Page - Renesas Technology Corp |
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270 / 646 page ![]() Section 11 Ethernet Controller (EtherC) Rev. 6.00 Jun. 12, 2007 Page 238 of 610 REJ09B0131-0600 11.3.4 PHY Interface Register (PIR) PIR is a 32-bit readable/writable register that provides a means of accessing the PHY registers via the MII. Bit Bit Name Initial Value R/W Description 31 to 4 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 3 MDI Undefined R MII Management Data-In Indicates the level of the MDIO pin. 2 MDO 0 R/W MII Management Data-Out Outputs the value set to this bit from the MDIO pin, when the MMD bit is 1. 1 MMD 0 R/W MII Management Mode Specifies the data read/write direction with respect to the MII. 0: Read direction is indicated 1: Write direction is indicated 0 MDC 0 R/W MII Management Data Clock Outputs the value set to this bit from the MDC pin and supplies the MII with the management data clock. For the method of accessing the MII registers, see section 11.4.4, Accessing MII Registers. |
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