HD6417618 datasheet(162/646 Pages) RENESAS

162 / 646 page

Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 130 of 610

REJ09B0131-0600

SDRAM:

• CS3WCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 15



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

WTRP1

WTRP0

R/W

Wait Cycle Number for Precharge Completion

Specify the number of minimum wait cycles inserted to

wait for the completion of precharge in the following

cases.

• From the start of auto-precharge to the issuing of the

ACTV command for the same bank.

• From the issuing of the PRE/PALL command to the

issuing of the ACTV command for the same bank.

• From the issuing of the PALL command during

auto-refreshing to the issuing of the REF command.

• From the issuing of the PALL command during

self-refreshing to the issuing of the SELF command.

00: 0 cycle (no wait cycle)

01: 1 cycle

10: 2 cycles

11: 3 cycles



Reserved

This bit is always read as 0. The write value should

always be 0.

WTRCD1

WTRCD0

R/W

Wait Cycle Number from ACTV Command to

READ(A)/WRIT(A) Command

Specify the number of minimum wait cycles from issuing

the ACTV command to issuing the READ(A)/WRIT(A)

command.

00: 0 cycle (no wait cycle)

01: 1 cycle

10: 2 cycles

11: 3 cycles

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