HD6417618 datasheet(163/646 Pages) RENESAS

163 / 646 page

Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 131 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

A3CL1

A3CL0

R/W

CAS Latency for Area 3.

Specify the CAS latency for area 3.

00: 1 cycle

01: 2 cycles

10: 3 cycles

11: Reserved (setting prohibited)

6, 5



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

TRWL1

TRWL0

R/W

Wait Cycle Number for Precharge Start Wait

Specify the number of minimum wait cycles inserted to

wait for the start of precharge in the following cases.

• From the issuing of the WRITA command by this LSI

to the start of the auto-precharge in the SDRAM.

The ACTV command for the same bank is issued

after issuing the WRITA command in non-bank active

mode.

To confirm how many cycles should be needed in the

SDRAM between receiving the WRITA command and

the auto-precharge start, refer to the data sheets for

each SDRAM. Set this bit so that the cycle number in

that data sheets should not exceed the cycle number

set by this bit.

• From the issuing of the WRIT command by this LSI to

the issuing of the PRE command.

A different row address in the same bank is accessed

in bank active mode.

00: 0 cycle (no wait cycle)

01: 1 cycle

10: 2 cycles

11: 3 cycles

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