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HD6417618 Datasheet(PDF) 165 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 165 Page - Renesas Technology Corp |
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165 / 646 page  Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 133 of 610 REJ09B0131-0600 Bit Bit Name Initial Value R/W Description 19 to 15 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 14 13 12 11 TED3 TED2 TED1 TED0 0 0 0 0 R/W R/W R/W R/W Delay from Address to RD or WE Assert Specify the delay time from address output to RD or WE assertion in PCMCIA interface. 0000: 0.5 cycles 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: Reserved (setting prohibited) 1001: Reserved (setting prohibited) 1010: Reserved (setting prohibited) 1011: Reserved (setting prohibited) 1100: Reserved (setting prohibited) 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) |
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