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HD6417618 Datasheet(PDF) 158 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 158 Page - Renesas Technology Corp |
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158 / 646 page ![]() Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 126 of 610 REJ09B0131-0600 • CS5BWCR Bit Bit Name Initial Value R/W Description 31 to 19 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 18 17 16 WW2 WW1 WW0 0 0 0 R/W R/W R/W Number of Write Access Wait Cycles Specify the number of cycles that are necessary for write access. 000: Same number of cycles as WR3 to WR0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 11 SW1 SW0 0 0 R/W R/W Number of Delay Cycles from Address, CSn Assertion to RD, WEn (BEn) Assertion Specify the number of delay cycles from address and CSn assertion to RD and WEn (BEn) assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles |
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