HD6417618 datasheet(154/646 Pages) RENESAS

154 / 646 page

Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 122 of 610

REJ09B0131-0600

• CS3WCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to 21



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

BAS

R/W

Byte Access Selection for Byte-Selection SRAM

Specifies the

WEn (BEn) and RD/WR signal timing when

the byte-selection SRAM interface is used.

0: Asserts the

WEn (BEn) signal at the read/write timing

(signal used as strobe) and asserts the RD/

WR signal

during the write access cycle (signal used as status)

1: Asserts the

WEn (BEn) signal during the read/write

access cycle (used as status) and asserts the RD/

signal at the write timing (used as strobe)

19 to 11



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

WR3

WR2

WR1

WR0

R/W

Number of Access Wait Cycles

Specify the number of wait cycles that are necessary for

read access.

0000: 0 cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

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