HD6417618 datasheet(148/646 Pages) RENESAS

148 / 646 page

Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 116 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

IWRWD1

IWRWD0

R/W

Idle Cycles for Another Space Read-Write

Specify the number of idle cycles to be inserted after the

access to a memory that is connected to the area. The

read and write cycles which are performed consecutively

and are accessed to different areas are the target cycle.

000: No idle cycle inserted

001: 1 idle cycles inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted



Reserved

This bit is always read as 0. The write value should

always be 0.

IWRWS1

IWRWS0

R/W

Idle Cycles for Read-Write in Same Space

Specify the number of idle cycles to be inserted after the

access to a memory that is connected to the area. The

read and write cycles which are performed consecutively

and are accessed to the same area are the target cycle.

000: No idle cycle inserted

001: 1 idle cycles inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted



Reserved

This bit is always read as 0. The write value should

always be 0.

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