HD6417618 datasheet(146/646 Pages) RENESAS

146 / 646 page

Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 114 of 610

REJ09B0131-0600

7.4.1

Common Control Register (CMNCR)

CMNCR is a 32-bit register that controls the common items for each area. Do not access external

memory other than area 0 until setting CMNCR is complete.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 13



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

MAP

R/W

Space Specification

Selects the address map for the external address space.

The address maps to be selected are shown in tables 7.2

and 7.3.

0: Selects address map 1

1: Selects address map 2

11 to 5



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.



Reserved

This bit is always read as 1. The write value should

always be 1.

ENDIAN

0/1*

Endian Flag

Fetches the external pin (MD5) state for specifying

endian at a power-on reset. The endian setting for all the

address spaces are set by this bit. This is a read-only bit.

0: External pin (MD5) for specifying endian was driven

low at a power-on reset. This LSI is operated as big

endian.

1: External pin (MD5) for specifying endian was driven

high at a power-on reset. This LSI is being operated as

little endian.



Reserved

This bit is always read as 1. The write value should

always be 1.

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