HD6417618 datasheet(147/646 Pages) RENESAS

147 / 646 page

Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 115 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

HIZMEM

R/W

Hi-Z Memory Control

Specifies the pin state in standby mode for pins A25 to

A0,

BS, CSn, RD/WR, WEn (BEn)/DQMxx, and RD.

0: High impedance in standby mode

1: Driven in standby mode

HIZCNT

R/W

Hi-Z Control

Specifies the pin state in standby mode for the CKIO,

CKE,

RAS, and CAS pins.

0: High impedance in standby mode

1: Driven in standby mode

Note:

The external pin (MD5) state for specifying endian is sampled at a power-on reset.

When big endian is specified, this bit is read as 0 and when little endian is specified, this

bit is read as 1.

7.4.2

CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5B, 6B)

CSnBCR specifies the type of memory connected to each space, data-bus width of each space, and

the number of wait cycles between access cycles.

Do not access external memory other than area 0 until setting CSnBCR is completed.

Bit

Bit Name

Initial

Value

R/W

Description

31, 30



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

IWW1

IWW0

R/W

Idle Cycles between Write-Read Cycles and Write-Write

Cycles

Specify the number of idle cycles to be inserted after the

access to a memory that is connected to the area. The

write and read cycles or write and write cycles performed

consecutively are the target cycle.

000: No idle cycle inserted

001: 1 idle cycle inserted

010: 2 idle cycles inserted

011: 4 idle cycles inserted

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