HD6417618 datasheet(511/646 Pages) RENESAS

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Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 479 of 610

REJ09B0131-0600

18.2.9

Break Control Register (BRCR)

BRCR sets the following conditions:

• Channels A and B are used in two independent channel conditions or under the sequential

condition.

• A break is set before or after instruction execution.

• Specify whether to include the number of execution times on channel B in comparison

conditions.

• Specify whether to include data bus on channel B in comparison conditions.

• Enable PC trace.

The break control register (BRCR) is a 32-bit readable/writable register that has break conditions

match flags and bits for setting a variety of break conditions.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 16

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SCMFCA

R/W

L Bus Cycle Condition Match Flag A

When the L bus cycle condition in the break conditions

set for channel A is satisfied, this flag is set to 1 (not

cleared

to 0). In order to clear this flag, write 0 into this bit.

0: The L bus cycle condition for channel A does not

match

1: The L bus cycle condition for channel A matches

SCMFCB

R/W

L Bus Cycle Condition Match Flag B

When the L bus cycle condition in the break conditions

set for channel B is satisfied, this flag is set to 1 (not

cleared

to 0). In order to clear this flag, write 0 into this bit.

0: The L bus cycle condition for channel B does not

match

1: The L bus cycle condition for channel B matches

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