HD6417618 datasheet(515/646 Pages) RENESAS

515 / 646 page

Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 483 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

30 to 28

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

27 to 0

BSA27 to

BSA0

Undefined

Branch Source Address

Store bits 27 to 0 of the branch source address.

18.2.12

Branch Destination Register (BRDR)

BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch

destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is

cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by

a power-on reset. Other bits are not initialized by a power-on reset. The four BRDR registers have

a queue structure and a stored register is shifted at every branch.

Bit

Bit Name

Initial

Value

R/W

Description

DVF

BRDR Valid Flag

Indicates whether or not the branch source address is

stored. When a branch is made, this flag is set to 1.

This flag is cleared to 0 by one of the following

conditions: when this flag is read from this register,

when PC trace is enabled, and when a power-on reset

is generated.

0: The value of BRDR register is invalid

1: The value of BRDR register is valid

30 to 28

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

27 to 0

BDA27 to

BDA0

Undefined

Branch Destination Address

Store bits 27 to 0 of the branch destination address.

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