HD6417618 datasheet(519/646 Pages) RENESAS

519 / 646 page

Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 487 of 610

REJ09B0131-0600

• When a break after execution is selected:

The PC value saved is the address of the instruction to be executed following the instruction in

which the break condition matches. The fetched instruction is executed, and a break occurs

before the execution of the next instruction.

• When an address in a data access cycle is specified as a break condition:

The PC value is the address of the instruction to be executed following the instruction that

matched the break condition. The instruction that matched the condition is executed and the

break occurs before the next instruction is executed.

• When an address and data in a data access cycle are specified as a break condition:

The PC value is the start address of the instruction that follows the instruction already executed

when break processing started. When a data value is added to the break conditions, the break

will occur before the execution of an instruction that is within two instructions of the

instruction that matched the break condition. Therefore, where the break will occur cannot be

specified exactly.

18.3.6

PC Trace

• Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, and

interrupt) is generated, the branch source address and branch destination address are stored in

BRSR and BRDR, respectively.

• The branch source address has different values due to the kind of branch.

 Branch instruction

The branch instruction address.

 Interrupt and exception

The address of the instruction in which the interrupt or exception was accepted. This

address is equal to the return address saved onto the stack.

The start address of the interrupt or exception handling routine is stored in BRDR.

The TRAPA instruction belongs to interrupt and exception above.

• BRSR and BRDR have four pairs of queue structures. The top of queues is read first when the

address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read

BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the

PCTE bit (in BRCR) off and on, the values in the queues are invalid.

HD6417618 Datasheet(PDF) 519 Page - Renesas Technology Corp