HD6417618 datasheet(520/646 Pages) RENESAS

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Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 488 of 610

REJ09B0131-0600

18.3.7

Usage Examples

Break Condition Specified for L Bus Instruction Fetch Cycle:

• Register specifications

BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010,

BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000,

BRCR = H'00300400

Specified conditions: Channel A/channel B independent mode

 Channel A

Address: H'00000404, Address mask: H'00000000

Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not

included in the condition)

 Channel B

Address: H'00008010, Address mask: H'00000006

Data: H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not

included in the condition)

A user break occurs after an instruction of address H'00000404 is executed or before

instructions of addresses H'00008010 to H'00008016 are executed.

• Register specifications

BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E,

BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000,

BRCR = H'00000008

Specified conditions: Channel A/channel B sequential mode

 Channel A

Address: H'00037226, Address mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/word

 Channel B

Address: H'0003722E, Address mask: H'00000000

Data: H'00000000, Data mask: H'00000000

Bus cycle: L bus/instruction fetch (before instruction execution)/read/word

After address H'00037226 is executed, a user break occurs before an instruction of address

H'0003722E is executed.

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