HD6417618 datasheet(507/646 Pages) RENESAS

507 / 646 page

Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 475 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

Value

R/W

Description

IDA1

IDA0

R/W

Instruction Fetch/Data Access Select A

Select the instruction fetch cycle or data access cycle as

the bus cycle of the channel A break condition.

00: Condition comparison is not performed

01: The break condition is the instruction fetch cycle

10: The break condition is the data access cycle

11: The break condition is the instruction fetch cycle or

data access cycle

RWA1

RWA0

R/W

Read/Write Select A

Select the read cycle or write cycle as the bus cycle of the

channel A break condition.

00: Condition comparison is not performed

01: The break condition is the read cycle

10: The break condition is the write cycle

11: The break condition is the read cycle or write cycle

SZA1

SZA0

R/W

Operand Size Select A

Select the operand size of the bus cycle for the channel A

break condition.

00: The break condition does not include operand size

01: The break condition is byte access

10: The break condition is word access

11: The break condition is longword access

18.2.4

Break Address Register B (BARB)

BARB is a 32-bit readable/writable register. BARB specifies the address used for a break

condition in channel B.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BAB31 to

BAB 0

All 0

R/W

Break Address B

Stores an address of LAB or IAB which specifies a break

condition in channel B.

HD6417618 Datasheet(PDF) 507 Page - Renesas Technology Corp

HD6417618 Datasheet(HTML) 507 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL