HD6417618 datasheet(503/646 Pages) RENESAS

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Section 18 User Break Controller (UBC)

UBCS300C_0000200309000

Rev. 6.00 Jun. 12, 2007 Page 471 of 610

REJ09B0131-0600

Section 18 User Break Controller (UBC)

The user break controller (UBC) provides functions that simplify program debugging. These

functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug

programs without using an in-circuit emulator. Break conditions that can be set in the UBC are

instruction fetch or data read/write access, data size, data contents, address value, and stop timing

in the case of instruction fetch.

18.1

Features

The UBC has the following features:

• The following break comparison conditions can be set.

Number of break channels: two channels (channels A and B)

User break can be requested as either the independent or sequential condition on channels A

and B (sequential break: when channel A and channel B match with break conditions in the

different bus cycles in that order, a break condition is satisfied).

 Address (Compares addresses 32 bits):

Comparison bits are maskable in 1-bit units; user can mask addresses at lower 12 bits (4-k

page), lower 10 bits (1-k page), or any size of page, etc.

One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be

selected.

 Data (only on channel B, 32-bit maskable)

One of the two data buses (logic data bus (LDB) and internal data bus (IDB)) can be

selected.

 Bus cycle: Instruction fetch or data access

 Read/write

 Operand size: Byte, word, or longword

• User break interrupt is generated upon satisfying break conditions. A user-designed user-break

condition interrupt exception processing routine can be run.

• In an instruction fetch cycle, it can be selected that a break is set before or after an instruction

is executed.

• Maximum repeat times for the break condition (only for channel B): 212 – 1 times.

• Four pairs of branch source/destination buffers.

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