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HD6417618 Datasheet(PDF) 504 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 504 Page - Renesas Technology Corp |
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504 / 646 page  Section 18 User Break Controller (UBC) Rev. 6.00 Jun. 12, 2007 Page 472 of 610 REJ09B0131-0600 Figure 18.1 shows a block diagram of the UBC. BBRA BARA BAMRA CPU state signal IAB LAB MDB Access comparator Address comparator Channel A Access comparator Address comparator Data comparator PC trace Control Channel B BBRB BETR BARB BAMRB BBRB BDMRB BRSR BRDR BRCR User break request UBC location LDB/IDB Access control BBRA: Break bus cycle register A BARA: Break address register A BAMRA: Break address mask register A BBRB: Break bus cycle register B BARB: Break address register B BAMRB: Break address mask register B BDRB: Break data register B BDMRB: Break data mask register B BETR: Execution times break register BRSR: Branch source register BRDR: Branch destination register BRCR: Break control register [Legend] Figure 18.1 Block Diagram of UBC |
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