HD6417618 datasheet(509/646 Pages) RENESAS

509 / 646 page

Section 18 User Break Controller (UBC)

Rev. 6.00 Jun. 12, 2007 Page 477 of 610

REJ09B0131-0600

18.2.7

Break Data Mask Register B (BDMRB)

BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data

specified by BDRB.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BDMB31 to

BDMB 0

All 0

R/W

Break Data Mask B

Specifies bits masked in the break data of channel B

specified by BDRB (BDB31 to BDB0).

0: Break data BDBn of channel B is included in the

break condition

1: Break data BDBn of channel B is masked and is not

included in the break condition

Note: n = 31 to 0

Notes: 1. Specify an operand size when including the value of the data bus in the break condition.

2. When the byte size is selected as a break condition, the same byte data must be set in

bits 15

−8 and 7−0 in BDMRB as the break mask data.

18.2.8

Break Bus Cycle Register B (BBRB)

Break bus cycle register B (BBRB) is a 16-bit readable/writable register, which specifies (1) L bus

cycle or I bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in

the break conditions of channel B.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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