HD6417618 datasheet(449/646 Pages) RENESAS

449 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 417 of 610

REJ09B0131-0600

External Device

This LSI

No.

CPU

DMAC

HIF

CPU

Write to end

address of bank

0 in HIFRAM

completes and

operation halts

→ HIF bank

interrupt

occurs

→ HIFRAM bank switching

by HIF bank interrupt

handler (external device

accesses bank 1 and on-

chip CPU accesses

bank 0)

Re-activate

DMAC

← Assert

HIFDREQ

← Set DTRG bit to 1

Hereafter No. 11 to 13 are repeated. When a register other than HIFDATA is accessed (except

that HIFGSR read with HIFRS = low), HIFRAM consecutive write is interrupted, and No. 3 to 6

need to be done again.

Table 15.5

Consecutive Read Procedure from HIFRAM by External DMAC

External Device

This LSI

No.

CPU

DMAC

HIF

CPU

HIF initial setting

DMAC initial setting

Set HIFADR to

HIFRAM start

address

Set HIFRAM

consecutive read with

address increment in

HIFMCR

Select HIFDATA

Write data to bank 1 in

HIFRAM

After writing data to end

address of bank 1 in

HIFRAM, perform

HIFRAM bank switching

(external device

accesses bank 1 and on-

chip CPU accesses

bank 0)

Activate DMAC

← Assert

HIFDREQ

← Set DTRG bit to 1

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