HD6417618 datasheet(452/646 Pages) RENESAS

452 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 420 of 610

REJ09B0131-0600

Table 15.6

Input/Output Control for HIF Pins

LSI

Status

Reset State by

RES Pin

Reset Canceled by

RES Pin

HIFMD

input

level

High

(Boot setting)

Low

(Non-boot

setting)

High

(After the reset

canceled by boot

setting)

Low

(After the reset canceled

by non-boot setting)

HIFEBL

input

level

Low

High

The HIFEBL pin

is a general input

port and the HIF

is not controlled

by the signal

input on this pin.

Low

High

General input port at the

initial state *

HIFRDY

output

control

Output

buffer:

(Low

output)

Output

buffer:

(Low

output)

General input port

Output

buffer:

Off

Output

buffer: On

(Sequence

output)

General input port at the

initial state*

HIFINT

output

control

Output

buffer:

Off

Output

buffer:

Off

General input port

Output

buffer:

Off

Output

buffer: On

(Sequence

output)

General input port at the

initial state*

HIFDREQ

output

control

Output

buffer:

Off

Output

buffer:

Off

General input port

Output

buffer:

Off

Output

buffer: On

(Sequence

output)

General input port at the

initial state*

HIFD 15

to HIFD0

I/O

control

I/O

buffer:

Off

I/O

buffer:

Off

General input port

I/O buffer:

Off

I/O buffer

controlled

according to

states of

HIFCS,

HIFWR,

and

HIFRD

General input port at the

initial state*

HIFCS

input

control

Input

buffer:

Off

Input

buffer:

Off

General input port

Input buffer:

Off

Input buffer:

General input port at the

initial state*

HIFRS

input

control

Input

buffer:

Off

Input

buffer:

Off

General input port

Input buffer:

Off

Input buffer:

General input port at the

initial state*

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