HD6417618 datasheet(448/646 Pages) RENESAS

448 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 416 of 610

REJ09B0131-0600

Table 15.4

Consecutive Write Procedure to HIFRAM by External DMAC

External Device

This LSI

No.

CPU

DMAC

HIF

CPU

HIF initial setting

DMAC initial setting

Set HIFADR to

HIFRAM end address

− 8

Select HIFDATA and

write dummy data (4

bytes) to HIFDATA

Set HIFRAM

consecutive write with

address increment in

HIFMCR

Select HIFDATA and

write dummy data (4

bytes) to HIFDATA

→

→ HIF bank

interrupt

occurs

→ HIFRAM bank switching

by HIF bank interrupt

handler (external device

accesses bank 1 and on-

chip CPU accesses

bank 0)

Activate DMAC

← Assert

HIFDREQ

← Set DTRG bit to 1

Consecutive

data write to

bank 1 in

HIFRAM

Write to end

address of bank

1 in HIFRAM

completes and

operation halts

→ HIF bank

interrupt

occurs

→ HIFRAM bank switching

by HIF bank interrupt

handler (external device

accesses bank 0 and on-

chip CPU accesses

bank 1)

Re-activate

DMAC

← Assert

HIFDREQ

← Set DTRG bit to 1

Consecutive

data write to

bank 0 in

HIFRAM

Read data from bank 1 in

HIFRAM

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