HD6417618 datasheet(447/646 Pages) RENESAS

Part #	HD6417618

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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447 / 646 page

Section 15 Host Interface (HIF)

Rev. 6.00 Jun. 12, 2007 Page 415 of 610

REJ09B0131-0600

When the external DMAC is specified to detect the rising edge of the HIFDREQ signal, set DMD

= 1 and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. Then after

writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is generated at the HIFDREQ

pin.

DTRG bit

DPOL bit

HIFDREQ

After assert, negated when

tPCYC (peripheral clock cycle)

× 32 cyc have elapsed.

Asserted in synchronization

with the DTRG bit being set

by the on-chip CPU.

The DTRG bit is cleared

simultaneously with

HIFDREQ negate.

Negated in synchronization

with the DPOL bit being set

by the on-chip CPU.

Figure 15.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1)

When the external DMAC supports intermittent operating mode (block transfer mode), efficient

data transfer can be implemented by using the HIFRAM consecutive access and bank functions.

HD6417618 Datasheet(PDF) 447 Page - Renesas Technology Corp