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HD6417618 Datasheet(PDF) 358 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 358 Page - Renesas Technology Corp |
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358 / 646 page  Section 14 Serial Communication Interface with FIFO (SCIF) Rev. 6.00 Jun. 12, 2007 Page 326 of 610 REJ09B0131-0600 • On-chip baud rate generator with selectable bit rates • Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external) • Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error interrupts are requested independently. • When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving power. • In asynchronous, on-chip modem control functions (RTS and CTS) (only for channel 1 and channel 0). • The number of data in the transmit and receive FIFO registers and the number of receive errors of the receive data in the receive FIFO register can be ascertained. • A time-out error (DR) can be detected when receiving in asynchronous mode. |
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