HD6417618 datasheet(362/646 Pages) RENESAS

362 / 646 page

Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 330 of 610

REJ09B0131-0600

14.3.1

Receive Shift Register (SCRSR)

SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received,

LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is

automatically transferred to SCFRDR, the receive FIFO data register. The CPU cannot read or

write to SCRSR directly.

14.3.2

Receive FIFO Data Register (SCFRDR)

SCFRDR is a 16-stage 8-bit FIFO register that stores serial receive data. The SCIF completes the

reception of one byte of serial data by moving the received data from the receive shift register

(SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored.

The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the

SCFRDR, the value is undefined. When this register is full of receive data, subsequent serial data

is lost.

SCFRDR is initialized to undefined value by a power-on reset.

Bit

Bit Name

Initial

value

R/W

Description

7 to 0



Undefined

FIFO for transmits serial data

14.3.3

Transmit Shift Register (SCTSR)

SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register

(SCFTDR) into SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After

transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into

SCTSR and starts transmitting again. The CPU cannot read or write to SCTSR directly.

HD6417618 Datasheet(PDF) 362 Page - Renesas Technology Corp