HD6417618 datasheet(363/646 Pages) RENESAS

363 / 646 page

Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 331 of 610

REJ09B0131-0600

14.3.4

Transmit FIFO Data Register (SCFTDR)

SCFTDR is a 16-stage 8-bit FIFO register that stores data for serial transmission. When the SCIF

detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the

SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed

until there is no transmit data left in SCFTDR. SCFTDR can always be written to by the CPU.

When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new

data is attempted, the data is ignored.

SCFTDR is initialized to undefined value by a power-on reset.

Bit

Bit Name

Initial

value

R/W

Description

7 to 0



Undefined

FIFO for transmits serial data

14.3.5

Serial Mode Register (SCSMR)

SCSMR is a 16-bit register that specifies the SCIF serial communication format and selects the

clock source for the baud rate generator.

The CPU can always read and write to SCSMR. SCSMR is initialized to H'0000 by a power-on

reset.

Bit

Bit Name

Initial

value

R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R/W

Communication Mode

Selects whether the SCIF operates in asynchronous or

synchronous mode.

0: Asynchronous mode

1: Synchronous mode

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