HD6417618 datasheet(357/646 Pages) RENESAS

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Section 14 Serial Communication Interface with FIFO (SCIF)

SCIS3C4A_000020030900

Rev. 6.00 Jun. 12, 2007 Page 325 of 610

REJ09B0131-0600

Section 14 Serial Communication Interface with FIFO

(SCIF)

14.1

Overview

This LSI has a three-channel serial communication interface with FIFO (SCIF) that supports both

asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for

both transmission and reception independently for each channel that enable this LSI to perform

efficient high-speed continuous communication.

14.1.1

Features

• Asynchronous serial communication:

 Serial data communication is performed by start-stop in character units. The SCIF can

communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous

communication interface adapter (ACIA), or any other communications chip that employs

a standard asynchronous serial system. There are eight selectable serial data

communication formats.

 Data length: 7 or 8 bits

 Stop bit length: 1 or 2 bits

 Parity: Even, odd, or none

 Receive error detection: Parity, framing, and overrun errors

 Break detection: Break is detected when a framing error is followed by at least one frame at

the space 0 level (low level). It is also detected by reading the RxD level directly from the

port data register when a framing error occurs.

• Synchronous mode:

 Serial data communication is synchronized with a clock signal. The SCIF can communicate

with other chips having a synchronous communication function. There is one serial data

communication format.

 Data length: 8 bits

 Receive error detection: Overrun errors

• Full duplex communication: The transmitting and receiving sections are independent, so the

SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so

high-speed continuous data transfer is possible in both the transmit and receive directions.

HD6417618 Datasheet(PDF) 357 Page - Renesas Technology Corp