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HD6417618 Datasheet(PDF) 188 Page - Renesas Technology Corp

Part # HD6417618
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series
PDF  646 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6417618 Datasheet(HTML) 188 Page - Renesas Technology Corp

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Section 7 Bus State Controller (BSC)
Rev. 6.00 Jun. 12, 2007 Page 156 of 610
REJ09B0131-0600
Table 7.11
Relationship between Register Settings and Address Multiplex Output (2)
Conditions: One 64-Mbit product (1 Mword x 16 bits x 4 banks, 8-bit column product) is
connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 01 (12-bit
row address), and A3COL[1:0] = 00 (8-bit column address).
Pins of this LSI
Output Row
Address
Output Column
Address
Pins of SDRAM Function
A17
A25
A17
Unused
A16
A24
A16
A15
A23
A15
A14
A22*
2
A22*
2
A13 (BA1)
Specifies bank
A13
A21*
2
A21*
2
A12 (BA0)
A12
A20
A12
A11
Address
A11
A19
L/H*
1
A10/AP
Specifies
address/precharge
A10
A18
A10
A9
Address
A9
A17
A9
A8
A8
A16
A8
A7
A7
A15
A7
A6
A6
A14
A6
A5
A5
A13
A5
A4
A4
A12
A4
A3
A3
A11
A3
A2
A2
A10
A2
A1
A1
A9
A1
A0
A0
A8
A0
Unused
Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the
access mode.
2. Bank address specification



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