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HD6417618 Datasheet(PDF) 187 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 187 Page - Renesas Technology Corp |
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187 / 646 page ![]() Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 155 of 610 REJ09B0131-0600 Table 7.10 Relationship between Register Settings and Address Multiplex Output (1) Conditions: One 16-Mbit product (512 kwords x 16 bits x 2 banks, 8-bit column product) is connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 00 (11-bit row address), and A3COL[1:0] = 00 (8-bit column address). Pins of this LSI Output Row Address Output Column Address Pins of SDRAM Function A17 A25 A17 Unused A16 A24 A16 A15 A23 A15 A14 A22 A14 A13 A21 A21 A12 A20* 2 A20* 2 A11 (BA0) Specifies bank A11 A19 L/H* 1 A10/AP Specifies address/precharge A10 A18 A10 A9 Address A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 A0 A8 A0 Unused Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the access mode. 2. Bank address specification |
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