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HD6417618 Datasheet(PDF) 186 Page - Renesas Technology Corp |
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HD6417618 Datasheet(HTML) 186 Page - Renesas Technology Corp |
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186 / 646 page ![]() Section 7 Bus State Controller (BSC) Rev. 6.00 Jun. 12, 2007 Page 154 of 610 REJ09B0131-0600 Figure 7.11 shows an example of the connection of the SDRAM with the LSI. A14 A1 CKE CKIO CSn RAS CAS RD/ WR D15 D0 DQMLU DQMLL 64-Mbit SDRAM (1 Mword x 16 bits x 4 banks) A13 A0 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML This LSI Figure 7.11 Example of 16-Bit Data-Width SDRAM Connection Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ1 and BSZ0 in CSnBCR, AnROW1 and AnROW0 and AnCOL1 AnCOL0 in SDCR. Tables 7.10 to 7.12 show the relationship between those settings and the bits output on the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address are always output on these pins. Pin A0 of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to pin A1 of this LSI; pin A1 pin of SDRAM to pin A2 of this LSI, and so on. |
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